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1 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e bicmos lvpecl clock generator ? device specification sonet/sdh/atm oc-12 transmitter and receiver S3035 features ? complies with bellcore and itu-t specifications ? on-chip high-frequency plls for clock generation and clock recovery ? supports 155.52 mbit/s (oc-3) and 622.08 mbit/s (oc-12) ? selectable reference frequencies of 19.44, 38.88, 51.84 or 77.76 mhz ? interface to both lvpecl and ttl logic ? redundant receiver inputs ? redundant transmitter outputs ? 8-bit ttl data path ? compact 14 mm 80 pin pqfp package ? diagnostic loopback mode ? lock detect ? low jitter lvpecl interface ? single 3.3 v supply applications ? sonet/sdh-based transmission systems ? sonet/sdh modules ? sonet/sdh test equipment ? atm over sonet/sdh ? section repeaters ? add drop multiplexers (adm) ? broad-band cross-connects ? fiber optic terminator ? fiber optic test equipment ? atm switch backbones requiring redundancy figure 1. system block diagram sonet/sdh/atm oc-3/12 transceiver w/cdr S3035 general description the S3035 sonet/sdh transceiver chip is a fully integrated serialization/deserialization sonet oc-12 (622.08 mbit/s) and oc-3 (155.52 mbit/s) in- terface device. the chip performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with sonet/sdh transmission stan- dards. the device is suitable for sonet-based atm applications. figure 1 shows a typical network appli- cation. on-chip clock synthesis is performed by the high- frequency phase-locked loop on the S3035 transceiver chip allowing the use of a slower external transmit clock reference. clock recovery is performed on the device by synchronizing its on-chip vco di rectly to the incoming data stream. the S3035 also per- forms sonet/sdh frame detection. the chip can be used with a 19.44, 38.88, 51.84 or 77.76 mhz refer- ence clock, in support of existing system clocking schemes. redundant transmit and receive serial i/o can be used to implement redundant physical layers in atm backbones. the low jitter lvpecl interface guarantees compli- ance with the bit-error rate requirements of the bellcore and itu-t standards. the S3035 is pack- aged in a 14 mm 80 pqfp, offering designers a small package outline. S3035 sonet/sdh transceiver network interface processor network interface processor S3035 sonet/sdh transceiver otx orx otx orx 8 8 8 8 otx orx orx otx
2 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e sonet overview synchronous optical network (sonet) is a stan- dard for connecting one fiber system to another at the optical level. sonet, together with the synchro- nous digital hierarchy (sdh) administered by the itu-t, forms a single international standard for fiber interconnect between telephone networks of differ- ent countries. sonet is capable of accommodating a variety of transmission rates and applications. the sonet standard is a layered protocol with four separate layers defined. these are: ? photonic ? section ? line ? path figure 2 shows the layers and their functions. each of the layers has overhead bandwidth dedicated to administration and maintenance. the photonic layer simply handles the conversion from electrical to opti- cal and back with no overhead. it is responsible for transmitting the electrical signals in optical form over the physical media. the section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. key functions of this layer are framing, scrambling, and error moni- toring. the line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. its main functions are synchronization, multiplexing, and reli- able transport. the path layer is responsible for the actual transport of services at the appropriate signal- ing rates. data rates and signal hierarchy table 1 contains the data rates and signal designa- tions of the sonet hierarchy. the lowest level is the basic sonet signal referred to as the synchronous transport signal level-1 (sts-1). an sts- n signal is made up of n byte-interleaved sts-1 signals. the optical counterpart of each sts- n signal is an opti- cal carrier level- n signal (oc- n ). the S3035 chip supports oc-3 and oc-12 rates (155.52 and 622.08 mbit/s). frame and byte boundary detection the sonet/sdh fundamental frame format for sts-12 consists of 36 transport overhead bytes fol- lowed by synchronous payload envelope (spe) bytes. this pattern of 36 overhead and 1044 spe bytes is repeated nine times in each frame. frame and byte boundaries are detected using the a1 and a2 bytes found in the transport overhead. (see figure 3.) for more details on sonet operations, refer to the bellcore sonet standard document. elec. itu-t optical data rate (mbit/s) sts-1 oc-1 51.84 sts-3 stm-1 oc-3 155.52 sts-12 stm-4 oc-12 622.08 sts-24 stm-8 oc-24 1244.16 sts-48 stm-16 oc-48 2488.32 table 1. sonet signal hierarchy figure 2. sonet structure 0 bps end equipment payload to spe mapping maintenance, protection, switching optical transmission scrambling, framing fiber cable end equipment section layer photonic layer line layer path layer path layer section layer photonic layer line layer layer overhead (embedded ops channel) functions 576 kbps 192 kbps
3 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e figure 3. stsC12/ocC12 frame format 9 rows 12 a1 bytes 12 a2 bytes a1 a1 a1 a1 a2 a2 a2 a2 transport overhead 36 columns 36 x 9 = 324 bytes synchronous payload envelope 1044 columns 1044 x 9 = 9396 bytes 125 sec s s S3035 overview the S3035 transceiver implements sonet/sdh se- rialization/deserialization, transmission, and frame detection/recovery functions. the block diagram in figure 4 shows the basic operation of the chip. this chip can be used to implement the front end of sonet equipment, which consists primarily of the serial transmit interface and the serial receive inter- face. the chip handles all the functions of these two elements, including parallel-to-serial and serial-to-par- allel conversion, clock generation and recovery, and system timing. the system timing circuitry consists of management of the data stream, framing, and clock distribution throughout the front end. the S3035 is divided into a transmitter section and a receiver section. the sequence of operations is as follows: amcc congo (s1201) pos/atm sonet mapper amcc nile (s1202) atm sonet mapper suggested interface devices transmitter operations: 1. 8-bit parallel input 2. parallel-to-serial conversion 3. redundant serial output receiver operations: 1. redundant serial input select 2. clock and data recovery from serial input 3. frame detection 4. serial-to-parallel conversion 5. 8-bit parallel output internal clocking and control functions are transpar- ent to the user. a lock detect feature is provided on the S3035, which indicates that the pll is locked (synchronized) to the incoming data stream, and facilitates continu- ous down-stream clocking in the absence of data.
4 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e 1:8 serial to parallel timing gen m u x clock recovery testen frame byte detect dleb rsd0p/n rsd1p/n rsdsel oof fp pout[7:0] 8 sdttl backup reference gen poclk rxlockdet 8 pin[7:0] 8:1 parallel to serial tsd1p/n oe1 piclk timing gen pclk 38mhzclk 51mhzclk clock synthesizer rstb tstrst mode 0 mode 1 cap1 cap2 transmitter receiver lleb slptime refclkp/n ttlref sdpecl tsd0p/n oe0 m u x 19mhzclk d d figure 4. S3035 transceiver functional block diagram
5 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e S3035 transceiver functional description transmitter operation the S3035 transceiver chip performs the serializing stage in the processing of a transmit sonet sts-3 or sts-12 bit serial data stream. it converts the 8-bit parallel 19.44 or 77.76 mbps data stream into bit serial format at 155.52 or 622.08 mbit/sec. a high-frequency bit clock can be generated from a 19.44 or 77.76 mhz frequency reference by using an integral frequency synthesizer consisting of a phase- locked loop circuit with a divider in the loop. diagnostic loopback is provided (transmitter to re- ceiver). see other operating modes. clock synthesizer the clock synthesizer, shown in the block diagram in figure 4, is a monolithic pll that generates the se- rial output clock phase synchronized with the input reference clock (refclkp/n or ttlref). the refclkp/n or ttlref input must be gener- ated from a crystal oscillator which has a frequency accuracy that meets the value stated in table 7 in order for the tsd frequency to have the same accu- racy required for operation in a sonet system. lower accuracy crystal oscillators may be used in applications less demanding than sonet/sdh. the on-chip pll consists of a phase detector, which compares the phase relationship between the vco output and the refclkp/n or ttlref input, a loop filter which converts the phase detector output into a smooth dc voltage, and a vco, whose frequency is varied by this voltage. the loop filter generates a vco control voltage based on the average dc level of the phase discrimi- nator output pulses. a single external clean-up capacitor is utilized as part of the loop filter. the loop filters corner frequency is optimized to minimize out- put phase jitter. timing generation the timing generation function, seen in figure 4, provides a byte rate version of the transmit serial clock. this circuitry also provides an internally gen erated load signal, which transfers the pin[7:0] data from the parallel input register to the serial shift register. the pclk output is a byte rate version of transmit serial clock at 19.44 or 77.76 mhz. pclk is intended for use as a byte speed clock for upstream multiplex- ing and overhead processing circuits. using pclk for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3035 device. parallel-to-serial converter the parallel-to-serial converter shown in figure 4 is comprised of two byte-wide registers. the first regis- ter latches the data from the pin[7:0] bus on the rising edge of piclk. the second register is a paral- lel loadable shift register which takes its parallel input from the first register. the load signal, which latches the data from the par- allel to the serial shift register, has a fixed relationship to pclk. if piclk is tied to pclk, the pin[7:0] data latched into the parallel register will meet the timing specifications with respect to the load signal. if piclk is not tied to pclk, the delay must meet the timing requirements shown in figure 8. e d o m ] 0 : 1 [] 0 : 1 [ ] 0 : 1 [ ] 0 : 1 [] 0 : 1 [ k c o l c e c n e r e f e r y c n e u q e r fy c n e u q e r f y c n e u q e r f y c n e u q e r fy c n e u q e r f g n i t a r e p o e d o me d o m e d o m e d o me d o m 0 0z h m 4 4 . 9 12 1 - s t s 1 0z h m 8 8 . 8 32 1 - s t s 0 1z h m 4 8 . 1 52 1 - s t s 1 1z h m 6 7 . 7 72 1 - s t s c n 0z h m 4 4 . 9 13 - s t s c n 1z h m 8 8 . 8 33 - s t s 0 c nz h m 4 8 . 1 53 - s t s 1 c nz h m 6 7 . 7 73 - s t s 1 table 2. reference frequency options table 3. reference jitter limits 1. only valid in slp mode. y c n e u q e r f d n a b r e t t i j k c o l c e c n e r e f e r m u m i x a m g n i t a r e p o e d o m z h m 5 o t z h k 2 1s m r s p 4 12 1 C s t s z h m 1 o t z h k 2 1s m r s p 6 53 C s t s
6 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e frequency stability without incoming data is guaran- teed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by greater than the value specified in table 7 with respect to refclkp/ n, the pll will be declared out of lock, and the pll will lock to the reference clock. the assertion of los will also cause an out of lock condition. the loop filter transfer function is optimized to en- able the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. this transfer function yields the typical capture time stated in table 7 for random incoming nrz data. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance proposed for sonet equipment by the bellcore ta-nwt-000253 standard, shown in figure 5. lock detect the S3035 contains a lock detect circuit which moni- tors the integrity of the serial data inputs. if the received serial data fails the run length or frequency test, the pll will be forced to lock to the local refer- ence clock. this will maintain the correct frequency of the poclk output under loss of signal or loss of lock conditions. if the serial data inputs have a run length of 80-bit times with no transitions, the pll will be declared out of lock. in addition, if the recovered clock frequency deviates from the local reference clock frequency by more than the specified ppm, the pll will also be declared out of lock. the lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. if the recovered clock fre- quency is determined to be within the specified ppm and the run length check indicates valid data, the pll will be declared in lock and the lock detect out- put will go active. see table 7. figure 5. clock recovery jitter tolerance 25k 65k 250k 6.5k 300 30 0.15 1.5 15 jitter frequency (hz) jitter amplitude (ul p-p) minimum proposed tolerance (ta-nwt-000253) oc-12 oc-3 clock recovery clock recovery, as shown in the block diagram in figure 4, generates a clock that is at the same fre- quency as the incoming data bit rate at the rsd input or, in loopback, the transmitter data output. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. out- put pulses from the discriminator indicate the required direction of phase corrections. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which gener- ates the recovered clock. receiver operation the S3035 transceiver chip provides the first stage of digital processing of a receive sonet sts-3 or sts-12 bit-serial stream. it converts the bit-serial 155.52 or 622.08 mbit/sec data stream into a 19.44 or 77.76 mbps 8-bit parallel data format. clock recovery is performed on the selected incom- ing serial scrambled nrz data stream. a 19.44 or 77.76 mhz reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. an integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. a loopback mode is provided for diagnostic loopback (transmitter to receiver).
7 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e backup reference generator the backup reference generator seen in figure 4 provides backup reference clock signals to the clock recovery block when the clock recovery block de- tects a loss of signal or out of lock condition. it contains a counter that divides the clock output from the clock recovery block down to the same fre- quency as the reference clock, refclkp/n. frame and byte boundary detection the frame and byte boundary detection circuitry searches the incoming data for three consecutive a1 bytes followed immediately by three consecutive a2 bytes. framing pattern detection is enabled and dis- abled by the out-of-frame (oof) input. detection is enabled by a rising edge on oof, and remains en- abled for the duration that oof is set high. it is disabled when a framing pattern is detected and oof is no longer set high. when framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (rsd or looped transmitter data). the timing generator block takes the located byte bound- ary and uses it to block the incoming data stream into bytes for output on the parallel output data bus (poutp/n[7:0]). the frame boundary is reported on the frame pulse (fp) output when any 48-bit pattern matching the framing pattern is detected on the in- coming data stream. when framing pattern detection is disabled, the byte boundary is frozen to the loca- tion found when detection was previously enabled. only framing patterns aligned to the fixed byte boundary are indicated on the fp output. the probability that random data in an sts-3 or sts- 12 stream will generate the 48-bit framing pattern is extremely small. it is highly improbable that a mimic pattern would occur within one frame of data. there- fore, the time to match the first frame pattern and to verify it with down stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 m s, even for extremely high bit error rates. once down stream overhead circuitry has verified that frame and byte synchronization are correct, the oof input can be set low to disable the frame search process from trying to synchronize to a mimic frame pattern serial-to-parallel converter the serial-to-parallel converter consists of three 8-bit registers. the first is a serial-in, parallel-out shift register, which performs serial-to-parallel con- version clocked by the clock recovery block. the second is an 8-bit internal holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte boundary detection block. on the falling edge of the free running poclk, the data in the holding register is transferred to an output holding register which drives pout[7:0]. the delay through the serial-to-parallel converter can vary from 1.5 to 3.5 byte periods (12 to 28 serial bit periods) measured from the first bit of an incom- ing byte to the beginning of the parallel output of that byte. the variation in the delay is dependent on the alignment of the internal parallel load timing, which is synchronized to the data byte boundaries, with re spect to the falling edge of poclk, which is independent of the byte boundaries. the advantage of this serial-to-parallel converter is that poclk is nei- ther truncated nor extended during reframe sequences. (see figure 10.)
8 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e other operating modes diagnostic loopback when the diagnostic loopback enable (dleb) input is active, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. sdpecl must be high for di- agnostic loopback. the differential serial output data from the transmitter is routed to the clock recovery unit and serial-to-par- allel block in place of the normal receive data stream (rsd). line loopback when line loopback enable (lleb) is active, a loopback from the receiver to the transmitter at the serial data rate can be set up for facility loopback testing. the recovered clock is used to retime the incoming data before driving the tsdp/n outputs. in line loopback mode, the tsclkp/n outputs will be driven by the receiver recovered clock. serial loop timing in serial loop timing mode (slptime), the clock synthesizer pll of the S3035 is bypassed, and the timing of the entire transmitter section is controlled by the recovered receive serial clock. this mode is entered by using the slptime input. in this mode the refclkp/n input is not used, and the mode[1:0] inputs are ignored for all transmit functions. it should be carefully noted that the inter- nal pll continues to operate in this mode, and continues as the source for the 38.51 mhzclk, and if this signal is being used, the refclkp/n and mode[1:0] inputs must be properly driven. forward clocking for both 77.78 mhz and 38.88 mhz reference op- eration, the S3035 operates in the forward clocking mode. the pll locks the pclk output of the trans- mitter section to the refclk with a fixed and repeatable phase relation. this allows the transmit- ter data source to also be the timing source for the serial clock synthesis. the rising edge of pclk is locked to the rising edge of refclkp, with a maximum delay of 8 to 10 nsec due to the pclk ttl output driver. for operation at 19.44 mhz and 51.84 mhz refer- ences, separate timing paths are used for pll control and pclk generation, and forward clocking is not recommended. looptime mode when serial looptime enable (slptime) is active, the serial recovered clock from the receiver will re- place the serial clock in the transmitter section.
9 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e table 4. S3035 transmitter pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 n i p 6 n i p 5 n i p 4 n i p 3 n i p 2 n i p 1 n i p 0 n i p l t t v li2 7 1 7 0 7 9 6 8 6 7 6 6 6 5 6 d e n g i l a , d r o w s p b m 4 4 . 9 1 r o s p b m 6 7 . 7 7 a . t u p n i a t a d l e l l a r a p t n a c i f i n g i s t s o m e h t s i ] 7 [ n i p . k c o l c t u p n i l e l l a r a p k l c i p e h t o t t i b t s r i f e h t , d r o w m c p h c a e f o 1 t i b o t g n i d n o p s e r r o c ( t i b o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s a e l e h t s i ] 0 [ n i p . ) d e t t i m s n a r t s i ] 0 : 7 [ n i p . ) d e t t i m s n a r t t i b t s a l e h t , d r o w m c p h c a e f o 8 t i b . k l c i p f o e g d e g n i s i r e h t n o d e l p m a s k l c i pl t t v li4 7y t u d % 0 5 y l l a n i m o n , z h m 4 4 . 9 1 r o 6 7 . 7 7 a . k c o l c t u p n i l e l l a r a p o t d e s u s i k l c i p . d e n g i l a s i ] 0 : 7 [ n i p h c i h w o t , k c o l c t u p n i e l c y c e h t n i r e t s i g e r g n i d l o h a o t n i s t u p n i n i p e h t n o a t a d e h t r e f s n a r t s e l p m a s k l c i p f o e g d e g n i s i r e h t . r e t r e v n o c l a i r e s - o t - l e l l a r a p e r a k l c i p f o s e g d e g n i s i r o w t , t e s e r r e t s a m a r e t f a . ] 0 : 7 [ n i p . h t a p a t a d l a n r e t n i e h t e z i l a i t i n i y l l u f o t d e r i u q e r 1 p a c 2 p a c g o l a n ai2 1 1 1 d n a r o t i c a p a c r e t l i f p o o l l a n r e t x e e h t . r o t i c a p a c r e t l i f p o o l e u l a v r o t i c a p a c e h t . s n i p e s e h t o t d e t c e n n o c e r a s r o t s i s e r s i t l o v 0 5 . c i r t c e l e i d r ' 7 x , e c n a r e l o t % 0 1 f 1 0 . 0 e b d l u o h s . ) e l b a t p e c c a s i t l o v 6 1 ( d e d n e m m o c e r p 0 d s t n 0 d s t . f f i d l c e p v l o1 2 2 2 m a e r t s a t a d l a i r e s l c e p v l l a i t n e r e f f i d . a t a d l a i r e s t i m s n a r t . e l u d o m r e t t i m s n a r t l a c i t p o n a o t d e t c e n n o c y l l a m r o n , s l a n g i s . 0 e o y b d e l b a n e p 1 d s t n 1 d s t . f f i d l c e p v l o5 2 4 2 m a e r t s a t a d l a i r e s l c e p v l l a i t n e r e f f i d . a t a d l a i r e s t i m s n a r t . e l u d o m r e t t i m s n a r t l a c i t p o n a o t d e t c e n n o c y l l a m r o n , s l a n g i s . 1 e o y b d e l b a n e 0 e ol t t v li3 7. s t u p t u o 0 d s t e h t s e l b a n e t u p n i s i h t n o h g i h a . e l b a n e t u p t u o 1 e ol t t v li7 1. s t u p t u o 1 d s t e h t s e l b a n e t u p n i s i h t n o h g i h a . e l b a n e t u p t u o k l c pl t t v lo6 7e h t g n i d i v i d y b d e t a r e n e g k c o l c e c n e r e f e r a . k c o l c l e l l a r a p e t a n i d r o o c o t d e s u y l l a m r o n s i t i . t h g i e y b k c o l c t i b l a n r e t n i 9 1 0 3 s e h t d n a c i g o l m a e r t s p u n e e w t e b s r e f s n a r t e d i w - e t y b . e c i v e d k l c z h m 8 3l t t v lo1 s a d e s u e b n a c h c i h w k c o l c z h m 8 8 . 8 3 a . t u p t u o k c o l c z h m 8 3 s i k c o l c s i h t . e c i v e d r e l l o r t n o c e h t y b e c r u o s k c o l c e l b a t s a t a s e t a r e p o d n a k c o l c l a i r e s t i m s n a r t e h t m o r f n w o d d e d i v i d . s e d o m g n i t a r e p o l l a r o f z h m 8 8 . 8 3 k l c z h m 1 5l t t v lo3 s a d e s u e b n a c h c i h w k c o l c z h m 4 8 . 1 5 a . t u p t u o k c o l c z h m 1 5 s i k c o l c s i h t . e c i v e d r e l l o r t n o c e h t y b e c r u o s k c o l c e l b a t s a t a s e t a r e p o d n a k c o l c l a i r e s t i m s n a r t e h t m o r f n w o d d e d i v i d . s e d o m g n i t a r e p o l l a r o f z h m 4 8 . 1 5 k l c z h m 9 1l t t v lo0 8s a d e s u e b n a c h c i h w k c o l c z h m 4 4 . 9 1 a . t u p t u o k c o l c z h m 9 1 s i k c o l c s i h t . e c i v e d r e l l o r t n o c e h t y b e c r u o s k c o l c e l b a t s a t a s e t a r e p o d n a k c o l c l a i r e s t i m s n a r t e h t m o r f n w o d d e d i v i d . s e d o m g n i t a r e p o l l a r o f z h m 4 4 . 9 1
10 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e table 5. S3035 receiver pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p 0 d s r n 0 d s r . f f i d l c e p v l i2 3 3 3 n a o t d e t c e n n o c y l l a m r o n s l a n g i s m a e r t s . a t a d l a i r e s e v i e c e r n o s n o i t i s n a r t m o r f d e r e v o c e r s i k c o l c a . e l u d o m r e v i e c e r l a c i t p o . s t u p n i 1 d s r r o 0 d s r e h t p 1 d s r n 1 d s r . f f i d l c e p v l i6 3 7 3 n a o t d e t c e n n o c y l l a m r o n s l a n g i s m a e r t s . a t a d l a i r e s e v i e c e r n o s n o i t i s n a r t m o r f d e r e v o c e r s i k c o l c a . e l u d o m r e v i e c e r l a c i t p o . s t u p n i 1 d s r r o 0 d s r e h t f o ol t t v li2 4n r e t t a p g n i m a r f e l b a n e o t d e s u r o t a c i d n i . e m a r f f o t u o c i g o l n o i t c e t e d n r e t t a p g n i m a r f e h t . 5 3 0 3 s e h t n i c i g o l n o i t c e t e d l i t n u d e l b a n e s n i a m e r d n a , f o o n o e g d e g n i s i r a y b d e l b a n e s i r e v e h c i h w , w o l t e s s i f o o n e h w r o d e t c e t e d s i y r a d n u o b e m a r f e s l u p m u m i n i m a h t i w l a n g i s s u o n o r h c n y s a n a s i f o o . r e g n o l s i ) . 2 1 d n a 1 1 s e r u g i f e e s ( . d o i r e p k l c o p e n o f o h t d i w l c e p d sl c e p v li7 2h g i h e v i t c a . n w o d - l l u p l a n r e t n i h t i w l c e p v l . t c e t e d l a n g i s l c e p v l k 0 1 d e d n e - e l g n i s a . 0 c i g o l t a d l e h s i l t t d s n e h w o t e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e b o t t u p n i s i l c e p d s n e h w . r e w o p l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i e b l l i w s n i p ) n / p d s r ( n i a t a d l a i r e s e h t n o a t a d e h t , e v i t c a n i , e v i t c a s i l c e p d s n e h w . o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i n e h w . y l l a m r o n d e s s e c o r p e b l l i w s n i p n / p d s r e h t n o a t a d d a e t s n i e l u d o m r e v i e c e r l a c i t p o e h t o t d e t c e n n o c e b o t s i l t t d s n a t n e m e l p m i o t h g i h d e i t e b d l u o h s l c e p d s n e h t , l c e p d s f o n a t n e m e l p m i o t d e t c e n n o c n u t f e l r o , t c e t e d l a n g i s w o l e v i t c a . t c e t e d l a n g i s h g i h e v i t c a l t t d sl t t v li6 2c i g o l ( d e t c e n n o c n u s i l c e p d s n e h w h g i h e v i t c a . t c e t e d l a n g i s d e d n e - e l g n i s a . 1 c i g o l t a d l e h s i l c e p d s n e h w w o l e v i t c a . ) 0 e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e b o t t u p n i l t t v l s i l t t d s n e h w . r e w o p l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i o t o t d e c r o f y l l a n r e t n i e b l l i w s n i p n / p d s r e h t n o a t a d e h t , e v i t c a n i n / p d s r e h t n o a t a d , e v i t c a s i l t t d s n e h w . o r e z t n a t s n o c a . y l l a m r o n d e s s e c o r p e b l l i w s n i p 7 t u o p 6 t u o p 5 t u o p 4 t u o p 3 t u o p 2 t u o p 1 t u o p 0 t u o p l t t v lo4 5 3 5 2 5 0 5 9 4 8 4 6 4 5 4 , d r o w s / t i b m 4 4 . 9 1 r o s / t i b m 6 7 . 7 7 a . s u b t u p t u o a t a d l e l l a r a p t s o m e h t s i ] 7 [ t u o p . k c o l c t u p t u o l e l l a r a p k l c o p e h t o t d e n g i l a t s r i f e h t , d r o w m c p h c a e f o 1 t i b o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s a e l e h t s i ] 0 [ t u o p . ) d e v i e c e r t i b s i ] 0 : 7 [ t u o p . ) d e v i e c e r t i b t s a l e h t , d r o w m c p h c a e f o 8 t i b o t . k l c o p f o e g d e g n i l l a f e h t n o d e t a d p u p fl t t v lo4 4a t a d g n i m o c n i e h t n i s e i r a d n u o b e m a r f s e t a c i d n i . e s l u p e m a r f s a , d e l b a n e s i n o i t c e t e d n r e t t a p g n i m a r f f i . ) d s r ( m a e r t s k l c o p e n o r o f h g i h s e s l u p p f , t u p n i f o o e h t y b d e l l o r t n o c d e t c e t e d s i g n i m a r f e h t g n i h c t a m e c n e u q e s t i b - 8 4 a n e h w e l c y c , d e l b a s i d s i n o i t c e t e d n r e t t a p g n i m a r f n e h w . s t u p n i d s r e h t n o e t y b r e t f a , m a e r t s a t a d g n i m o c n i e h t n e h w h g i h s e s l u p p f e h t n o d e t a d p u s i p f . n r e t t a p g n i m a r f e h t s e h c t a m , t n e m n g i l a . k l c o p f o e g d e g n i l l a f l e s d s rl t t v li9 1. s t u p n i l a i r e s 1 d s r r o 0 d s r e h t r e h t i e s t c e l e s . t c e l e s d s r . 0 d s r s t c e l e s w o l , 1 d s r s t c e l e s h g i h
11 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e table 5. S3035 receiver pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d k l c o pl t t v lo6 5% 0 5 y l l a n i m o n , z h m 4 4 . 9 1 r o 6 7 . 7 7 a . k c o l c t u p t u o l e l l a r a p ] 0 : 7 [ t u o p o t d e n g i l a s i t a h t k c o l c t u p t u o e t a r e t y b , e l c y c y t u d e h t n o d e t a d p u e r a p f d n a ] 0 : 7 [ t u o p . a t a d t u p t u o l a i r e s e t y b . k l c o p f o e g d e g n i l l a f t e d k c o l x rl t t v lo8 5e h t n e h w h g i h t e s s i t a h t r o t a c i d n i y r e v o c e r k c o l c . t c e t e d k c o l a t a d g n i m o c n i e h t o t n o d e k c o l s a h y r e v o c e r k c o l c l a n r e t n i . t u p t u o s u o n o r h c n y s a n a s i t e d k c o l x r . m a e r t s
12 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e table 6. S3035 common pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d n e t s e tl t t v li1 6e d i v o r p o t h g i h t e s . h g i h e v i t c a . l a n g i s e l b a n e k c o l c t s e t . s t s e t n o i t c u d o r p g n i r u d l l p e h t o t s s e c c a p k l c f e r n k l c f e r . f f i d l c e p v l i8 7 t i b l a n r e t n i e h t r o f e c n e r e f e r e h t s a d e s u t u p n i k c o l c e c n e r e f e r e n o c i g o l a o t d e t c e n n o c e b t s u m ( . r e z i s e h t n y s y c n e u q e r f k c o l c . ) d e s u s i f e r l t t f i e t a t s f e r l t tl t t v li6 e c n e r e f e r e h t s a d e s u e b n a c t a h t t u p n i . k c o l c e c n e r e f e r l t t d e i t e b t s u m ( . r e z i s e h t n y s y c n e u q e r f k c o l c t i b l a n r e t n i e h t r o f . ) d e s u s i n / p k l c f e r f i h g i h b e l dl t t v li0 4c i t s o n g a i d s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l c i t s o n g a i d e h t s e s u e c i v e d 5 3 0 3 s e h t , h g i h s i b e l d n e h w . k c a b p o o l s e s u e c i v e d 5 3 0 3 s e h t , w o l n e h w . s t u p n i ) d s r ( a t a d y r a m i r p l c e p d s . r e t t i m s n a r t e h t m o r f a t a d k c a b p o o l c i t s o n g a i d e h t . k c a b p o o l c i t s o n g a i d r o f h g i h e b t s u m b t s rl t t v li1 4s e z i l a i t i n i . w o l e v i t c a . e c i v e d e h t r o f t u p n i t e s e r . t e s e r r e t s a m e h t o t e r i u q c a o t l l p e h t s e c r o f d n a e t a t s n w o n k a o t e c i v e d e h t t a d e i l p p a e b d l u o h s s m 6 1 t s a e l t a f o t e s e r a . k c o l c e c n e r e f e r - e r o t l l p e h t e c r o f o t s e h s i w r e s u e h t r e v e n e h w d n a p u - r e w o p o t e r i u q c a e r o s l a l l i w 5 3 0 3 s e h t . k c o l c e c n e r e f e r e h t o t e r i u q c a r o f t n e c s e i u q d l e h s i t u p n i a t a d l a i r e s e h t f i k c o l c e c n e r e f e r e h t . s m 6 1 t s a e l t a b e l ll t t v li6 1n e h w . k c a b p o o l e n i l s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l e n i l m o r f a t a d l a i r e s d e m i t e r e h t e t u o r l l i w 5 3 0 3 s e h t , w o l s i b e l l . s t u p t u o r e t t i m s n a r t e h t o t n o i t c e s e v i e c e r e h t 1 e d o m 0 e d o m l t t v li2 6 3 6 e c n e r e f e r e h t t c e l e s o t d e s u . s t u p n i t c e l e s e d o m g n i t a r e p o . ) 2 e l b a t e e s ( d e e p s g n i t a r e p o e h t d n a y c n e u q e r f k c o l c t s r t s tl t t v li5 1l l p e h t f o s n o i t r o p t e s e r o t d e s u . h g i h e v i t c a . t u p n i t e s e r t s e t . n o i t a r e p o l a m r o n r o f w o l d l e h . g n i t s e t n o i t c u d o r p g n i r u d c c v e r o c x tC5y l p p u s r e w o p d n g e r o c x td n gC4 8 1 ) v 0 ( d n u o r g 0 d n g a 1 d n g a d n gC3 1 0 1 ) v 0 ( d n u o r g 0 c c v a 1 c c v a v 3 . 3 +C4 1 9 y l p p u s r e w o p c c v t u o x tC0 2y l p p u s r e w o p d n g t u o x td n g3 2) v 0 ( d n u o r g e m i t p l sl t t v li4 6o t d e s u . h g i h e v i t c a . t u p n i t c e l e s e m i t p o o l k c o l c l a i r e s d e s u e b o t n o i t c e s e v i e c e r e h t m o r f k c o l c d e r e v o c e r e h t e l b a n e . k c o l c t i m s n a r t d e z i s e h t n y s e h t f o e c a l p n i
13 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d c c v l t tv 3 . 3 +7 4 5 5 y l p p u s r e w o p d n g l t td n g3 4 1 5 ) v 0 ( d n u o r g c c v n i l t tv 3 . 3 +9 5y l p p u s r e w o p d n g n i l t td n g0 6) v 0 ( d n u o r g c c v e r o c x rv 3 . 3 +8 3y l p p u s r e w o p d n g e r o c x rd n g9 3) v 0 ( d n u o r g 0 c c v a x r 1 c c v a x r v 3 . 3 +8 2 1 3 y l p p u s r e w o p 0 d n g a x r 1 d n g a x r d n g9 2 0 3 ) v 0 ( d n u o r g c c v k l c s rv 3 . 3 +5 3y l p p u s r e w o p d n g k l c s rd n g4 3) v 0 ( d n u o r g c c v k l cv 3 . 3 +2y l p p u s r e w o p d n g k l cd n g9 7) v 0 ( d n u o r g d n g k l c pd n g8 7) v 0 ( d n u o r g c c v k l c pv 3 . 3 +5 7y l p p u s r e w o p c n7 5 7 7 d e t c e n n o c t o n table 6. S3035 common pin assignment and descriptions (continued)
14 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e figure 6. 80 pqfp package dimensions are in mm. device S3035 85?c 35?c/w max still air q ja still air thermal management
15 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 62 61 48 47 46 45 44 43 42 41 S3035 pinout (80 pin pqfp) poclk ttlvcc pout7 pout6 pout5 ttlgnd pout4 pout3 pout2 ttlvcc pout1 pout0 fp ttlgnd oof txoutgnd tsd1n tsd1p sdttl sdpecl rxavcc0 rxagnd0 rxagnd1 rxavcc1 rsd0p rsd0n tsd0p tsd0n 30 31 32 rsclkgnd rsclkvcc rsd1p 64 63 pclkvcc piclk oe0 pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 pclk slptime mode0 mode1 12 13 38mhzclk clkvcc 51mhzclk txcoregnd txcorevcc ttlref refclkn refclkp avcc1 agnd1 cap2 cap1 14 15 16 agnd0 top view avcc0 testen rstb oe1 tstrst lleb rsdsel txcoregnd pclkgnd nc 19mhzclk clkgnd ttlingnd ttlinvcc rxlockdet nc rsd1n rxcorevcc rxcoregnd dleb 17 18 19 20 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 txoutvcc figure 7. S3035 pinout assignments
16 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e table 7. performance specifications * noise on refclkp/n should be less than 14 ps rms in a jitter frequency band from 12 khz to 5 mhz. r e t e m a r a pn i mp y tx a ms t i n un o i t i d n o c o c v l a n i m o n y c n e u q e r f r e t n e c 8 0 . 2 2 6 % 2 1 z h m r e t t i j t u p t u o a t a d 2 1 - s t s . k l c . f e r z h m 4 4 . 9 1 - . k l c . f e r z h m 8 8 . 8 3 - k l c . f e r z h m 4 8 . 1 5 - . k l c . f e r z h m 6 7 . 7 7 - 3 - s t s k l c . f e r z h m 4 4 . 9 1 - k l c . f e r z h m 8 8 . 8 3 - . k l c . f e r z h m 4 8 . 1 5 - 7 0 0 . 0 6 0 0 . 0 5 0 0 . 0 4 0 0 . 0 3 0 0 . 0 2 0 0 . 0 2 0 0 . 0 ) s m r ( i uk c o l n i , r e t t i j s m r e c n a r e l o t r e t t i j 2 1 - s t s / 3 - s t s 4 . 0) p - p ( i u y c n e u q e r f k c o l c e c n e r e f e r * e c n a r e l o t 0 2 -0 2 +m p p t u p t u o t e n o s t e e m o t d e r i u q e r n o i t a c i f i c e p s y c n e u q e r f d n a 3 - s t s / 3 - c o 2 1 - s t s / 2 1 - c o e g n a r e r u t p a c e g n a r k c o l e m i t e r u t p a c 0 0 2 % 2 1 2 3 m p p c e s e c n e r e f e r d e x i f o t t c e p s e r h t i w y c n e u q e r f e m i t k c o l n o i t i s i u q c a 6 1c e s f o y t i s n e d n o i t i s n a r t m u m i n i m d e r e w o p y d a e r l a e c i v e d h t i w % 0 2 . k l c . f e r d i l a v d n a p u g n i n e p o e y e a t a d t u p n i0 3i u f o %0 1 x 1 n a h t s s e l r e b d e r u s a e m 2 1 - k c o l c e c n e r e f e r e l c y c y t u d t u p n i 0 30 7i u f o % l l a f & e s i r k c o l c e c n e r e f e r s e m i t 0 . 2s ne d u t i l p m a f o % 0 9 o t % 0 1 l l a f & e s i r t u p t u o l c e p v l s e m i t 0 5 4s p 0 5 , % 0 9 o t % 0 1 w , d a o l p a c f p 5 h c i h w t a e c n e r e f f i d y c n e u q e r f d e r a l c e d s i k c o l f o t u o e h t o t d e r a p m o c k l c f e r ( ) k c o l c o c v n w o d d e d i v i d 0 5 20 9 20 3 3m p p h c i h w t a e c n e r e f f i d y c n e u q e r f k c o l n i d e r a l c e d s i l l p e v i e c e r e h t o t d e r a p m o c k l c f e r ( ) k c o l c o c v n w o d d e d i v i d 0 5 20 9 20 3 3m p p l a i r e s f o h t g n e l n u r m u m i x a m s i k c o l f o t u o e r o f e b t u p n i a t a d d e r a l c e d 0 80 0 0 1i u. n / p d s r n o s n o i t i s n a r t o n
17 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e parameter description min typ units conditions v oh output high voltage (ttl) ?3.3v power supply ?3.3v power supply 2.1 2.2 2.0 0 -500 max v v v cc = min, i oh = -2.4 ma v cc = min, i oh = -.1 ma i cc supply current 300 360 ma outputs open, v cc = v cc max p d power dissipation 1.0 1.25 w outputs open, v cc = v cc max v ol output low voltage (ttl) ?3.3v power supply 0.5 v v cc = min, i ol = 2.4 ma v ih v il i ih i il input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) 5.5 0.8 50 -50 v v a a v in = 2.4 v v in = 0.5 v table 10. lvttl input/output dc characteristics table 8. absolute maximum ratings table 9. recommended operating conditions r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g o t t c e p s e r h t i w c c v n o e g a t l o v5 . 0 -0 . 5 +v n i p t u p n i l t t v l y n a n o e g a t l o v5 . 0 -5 . 5 +v n i p t u p n i l c e p v l y n a n o e g a t l o v0c c vv t n e r r u c k n i s t u p t u o l t t v l8a m t n e r r u c e c r u o s t u p t u o l t t v l8a m t n e r r u c e c r u o s t u p t u o l c e p v l d e e p s h g i h0 5a m r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a0 4 -5 8c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 4 -5 2 1 +c ? d n g o t t c e p s e r h t i w c c v n o e g a t l o v n o i t a r e p o v 3 . 35 3 1 . 33 . 35 6 4 . 3 v n i p t u p n i l t t v l y n a n o e g a t l o v05 . 5v n i p t u p n i l c e p v l y n a n o e g a t l o v00 . 2v esd ratings the S3035 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above 1500 v except pin3, pin11, pin12, and pin25. the following are the absolute maximum stress ratings for the S3035 device. stresses beyond those listed may cause permanent damage to the devices. absolute maximum ratings are stress ratings only and operation of the device at the maximums stated or any other conditions beyond those indicated in the recommended operating condi- tions of the document are not inferred. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
18 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u d t k l c i p k l c p m o r f y a l e d k l c i p05 . 5s n s t n i p k l c i p . t . r . w e m i t p u t e s ] 0 : 7 [ n i p5 . 1s n h t n i p k l c i p . t . r . w e m i t d l o h ] 0 : 7 [ n i p0 . 1s n table 12. transmitter ac timing characteristics table 11. lvpecl input/output dc characteristics parameter v il v ih v il v ih v ol v oh v od v id i ihd i ild input low voltage input high voltage input low voltage input high voltage output low voltage output high voltage guaranteed input low voltage for single-ended inputs guaranteed input high voltage for single-ended inputs guaranteed input low voltage for differential inputs guaranteed input high voltage for differential inputs 51 w termination to v cc -2 v 51 w termination to v cc -2 v differential output voltage differential input voltage v id = 500 mv v id = 500 mv -0.500 -0.500 0.390 0.200 0.500 v cc -2.000 v cc -1.225 v cc -1.441 v cc -0.570 v cc -2.000 v cc -0.700 v cc -1.750 v cc -0.450 v cc -2.000 v cc -1.500 v cc -1.210 v cc -0.670 volts volts volts volts volts volts volts volts a a 20.000 20.000 100 -100 1.400 1.330 output diff. voltage input diff. voltage diff. input high current diff. input low current i ih sd inputs have internal 24 k w to 1.8 v load resistor. sd inputs have internal 24 k w to 1.8 v load resistor. a single-ended input high current i il a single-ended input low current symbol min typ max unit conditions table 13. receiver ac timing characteristics r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u e l c y c y t u d k l c o p0 40 6% p t t u o p 3 - s t s @ y a l e d . p o r p d i l a v ] 0 : 7 [ t u o p o t w o l k l c o p 2 1 - s t s @ y a l e d . p o r p d i l a v ] 0 : 7 [ t u o p o t w o l k l c o p 8 - 3 - 0 1 s n s n s t t u o p k l c o p . t . r . w e m i t p u t e s p f d n a ] 0 : 7 [ t u o p4s n h t t u o p k l c o p . t . r . w e m i t d l o h p f d n a ] 0 : 7 [ t u o p3s n
19 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e figure 8. transmitter input timing ts pin td piclk th pin piclk pclk pin[7:0] 1. when a setup time is specified on lvttl signals between an input and a clock, the setup time is the time in nanoseconds from the 50% cross over point of the input to the 50% cross over point of the clock. 2. when a hold time is specified on lvttl signals between an input and a clock, the hold time is the time in nanoseconds from the 50% cross over point of the clock to the 50% cross over point of the input. figure 9. receiver output timing diagram pout[7:0]fp poclk th pout tp pout tp pout 50% ts pout th pout duty cycle min duty cycle max tp pout 70% max min min 30% notes on output timing: 1. output propagation delay time of lvttl outputs is the time in nanoseconds from the 50% point of the reference signal to the 30% or 70% point of the output. 2. maximum output propagation delays of lvttl outputs are measured with a 15 pf load on the outputs.
20 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e receiver framing figure 10 shows a typical reframe sequence in which a byte realignment is made. the frame and byte boundary detection is enabled by the rising edge of oof and remains enabled while oof is high. both boundaries are recognized upon receipt of the third a2 byte which is the first data byte to be reported with the correct byte alignment on the out- going data bus (pout[7:0]). concurrently, the frame pulse is set high for one poclk cycle. when interfacing with a section terminating device, the oof input remains high for one full frame after the first frame pulse while the section terminating device verifies internally that the frame and byte alignment are correct, as shown in figure 11. since at least one framing pattern has been detected since the rising edge of oof, boundary detection is dis- abled when oof is set low. the frame and byte boundary detection block is acti- vated by the rising edge of oof, and stays active until the first fp pulse or until oof goes low, which- ever occurs last. figure 11 shows a typical oof timing pattern which occurs when the S3035 is con- nected to a down stream section terminating device. oof remains high for one full frame after the first fp pulse. the frame and byte boundary detection block is active until oof goes low. figure 12 shows the frame and byte boundary detec- tion activation by a rising edge of oof, and deactivated by the first fp pulse. figure 10. frame and byte boundary detection note 1. range of input to output delay can be 1.5 to 2.5 poclk cycles figure 11. oof operation timing figure 12. alternate oof timing a1 a1 a1 a2 a2 a2 a2 a2 note 1 a1 a1 a1 a2 a2 a2 (28h) invalid data valid data recovered clock/ refclk oof rsd pout[7:0] poclk fp boundary detection enabled oof fp boundary detection enabled oof fp
21 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e S3035 with data clock synchronous to reference clock in some applications it is necessary to "forward clock" the data in a sonet/sdh system. in this ap- plication the reference clock from which the high speed serial clock is synthesized and the parallel data clock both originate from the same (usually ttl/cmos) clock source. this application note ex- plains how the amcc S3035 can be configured to operate in this mode. clock control logic description the timing control logic in the S3035 automatically generates an internal load signal which has a fixed relationship to the reference clock. the logic takes in to account the variation of the reference clock to the internal load signal over temperature and voltage. the connections required to implement the design are shown in figure 13. the setup and hold times for the piclk to the data must be met by the controller asic. it is recommended that the data on the falling edge of the output reference clock be latched in or- der to meet the required specifications. possible problems in order to meet the jitter generation specifications required by sonet, the jitter of the reference clock must be minimized. it may be difficult to meet the sonet jitter generation specifications using a refer- ence clock input with a ttl reference source. application note asic data pin[7:0] piclk refclk serial data S3035 8 output reference clock output data figure 13. S3035 with data clocked by reference clock
22 S3035 sonet/sdh/atm oc-3/12 transceiver w/cdr july 25, 2000 / revision e x xxxx x prefix device package ordering information amcc is a registered trademark of applied micro circuits corporation. copyright ? 2000 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr.,5 san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i - s5 3 0 3p f q p 0 8 C a

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